Embodiments of the present invention pertain to the field of displaying images. More particularly, the present invention relates to display of images from a tiled memory.
Providing high-quality images is a feature that is very popular in many devices. For example, many computers include cathode ray tube (CRTs) displays, liquid crystal displays (LCDs), light emitting polymer displays (LEPs), or organic or inorganic light emitting diode displays (LEDs). Typically, the displays are divided into thousands (or millions) of picture elements (pixels), arranged in rows and columns (i.e., scan lines). The pixels are so close together that they appear connected. Each pixel or a group of pixels may have one or more pixel attributes defining the characteristics of the pixel stored in a memory.
Conventional graphics systems use paged memory structures to store these pixel attributes relating to scan lines of the display. These conventional systems perform their data operations by traversing a first scan line of displayed pixels, then advancing to a second scan line of displayed pixels using the corresponding stored pixel attributes in the paged memory. The operation advances iteratively, scan line by scan line, until the entire screen is displayed.
Some modem graphics systems can organize a display screen and corresponding memory according to tiled memory techniques for reasons of 3-Dimensional (3-D) accelerator performance, as shown in FIGS. 1a and 1b, respectively.
FIG. 1a illustrates a display screen 100 having pixels that are divided, for example, among fifteen tiles 101-115. FIG. 1b illustrates a corresponding memory 120 that stores pixel attributes W0-W35 (e.g., words) associated with the pixels of tile 101. For simplicity, only some of the pixel attributes are shown in FIG. 1b. More specifically, pixel attributes for columns 0, 1 and 5 of tile 101 are shown. Representations similar to the one shown for tile 101 in FIG. 1b, can be made for the other tiles in FIG. 1a. Pixel attributes W0-W35 are sequentially stored in memory 120 in consecutive memory address locations 0-35. While memory 120 stores pixel attributes W0-W35 with a vertically tiled organization, pixel attributes associated with the pixels of a tile can be organized in memory as either horizontal tiles or vertical tiles. Attributes organized as vertical tiles means that pixel attributes of adjacent pixels on a vertical line of the display are in consecutive locations in memory. Attributes organized as horizontal tiles means that pixel attributes of adjacent pixels on a horizontal line of the display are in consecutive locations in memory.
As shown in FIG. 1b, pixel attribute W0 and pixel attribute W1 are sequentially stored in consecutive memory address locations 0 and 1, in memory 120, and contain the information needed to control the pixels of column 0, row 0, and column 0, row 1, respectively. Similarly, pixel attribute W5 and pixel attribute W6 are sequentially stored in consecutive memory address locations 5 and 6, in memory 120, and contain the information needed to control the pixels of column 0, row 5, and column 1, row 0, respectively.
Organization of the pixel attributes into vertical tiles or horizontal tiles results in two consecutive pixel attributes being associated with two different rows or horizontal lines of a display screen. Thus, accessing two or more pixel attributes from consecutive memory locations that are associated with two different lines of a display screen can be inefficient. For example, when a horizontal scan line is displayed, the pixel attribute associated with the current scan line being displayed will be used while the pixel attribute associated with the next scan line will be discarded. The discarded attributed will be re-fetched from memory when the scan line with which the pixel attribute is associated is actually displayed. This doubles the required bandwidth of the display stream.
More specifically, for example, when drawing the first horizontal scan line of display 100, pixel attributes W0 and W1 are retrieved from memory 120, if memory 120 has a granularity of two words. Pixel attribute W0 is used to display the pixel at column 0, row 0, and pixel attribute W1 is discarded since it is related to the second horizontal scan line. Next, pixel attributes W6 and W7 are retrieved from memory 120. Pixel attribute W6 is used to display the pixel at column 1, row 0, and pixel attribute W7 is discarded. This process continues until the first horizontal scan line has been completed. When drawing the second horizontal scan line of display 100, pixel attributes W0 and W1 are again retrieved from memory 120. However, in this case, pixel attribute W1 is used to display the pixel at column 0, row 1, and pixel attribute W0 is discarded. This process of retrieving the same two attributes twice and only displaying a pixel using one of the attributes is inefficient. While the inefficiency has been described for a memory having vertical tiling, the inefficiency would also occur when there is tiling having a first display orientation and a display engine that uses scanning for display in another orientation.